Timing performance of the design is verified taking account of temperature and supply voltage variation applied to the device and of the semiconductor fabrication process variation characterised by the manufacturer; static timing analysis with the necessary constraints and conditions is one acceptable means for digital parts. Physical testing in the operational environment is preferred, with post-layout netlist verification where needed (for example for internal features, timing, abnormal conditions or robustness), and coverage by means other than physical test justified.
This control maps to 1 controls across 1 other frameworks. If you already hold one of them, the evidence you collected for it is the starting point here rather than new work.
Every mapping shown was judged rather than inferred from wording similarity, and the ones that failed review are published too. See the coverage reports and what was rejected.
The graph holds this control, the 1 it maps to, and the evidence behind each claim, over MCP and REST.