For every custom device (PLD, FPGA or ASIC contributing to DAL A, B or C functions) the planning documents record its assurance level, whether it is simple or complex, and for a simple device the justification against the simplicity criteria: how simple and how many its functions and interfaces are, how simple its data or signal processing is, how independent its functions, blocks and stages are, and for digital logic whether it is synchronous, how many independent clocks, state machines, states and transitions it has and how independent the state machines are. A device not shown to be simple is complex, and one built from simple parts may still be complex.
This control maps to 1 controls across 1 other frameworks. If you already hold one of them, the evidence you collected for it is the starting point here rather than new work.
Every mapping shown was judged rather than inferred from wording similarity, and the ones that failed review are published too. See the coverage reports and what was rejected.
The graph holds this control, the 1 it maps to, and the evidence behind each claim, over MCP and REST.