PLDs combine configurable I/O, non-fixed functions (logic blocks and user memory configured through a configuration technology), signal routing and fixed logic functions such as CPUs, memory controllers, clock, power and reset circuitry; users configure them with tools from simple to full development suites, program them once or many times, in volatile or non-volatile technologies whose safety-related capabilities differ (Flash, antifuse, SRAM); the guidance gives the failure modes of PLDs, notes on safety analyses covering the configuration and the user design, examples of safety mechanisms, the avoidance of systematic faults in the PLD design flow including tool confidence, an example of safety documentation and an example of safety analysis for a PLD.
The graph holds this control, the 0 it maps to, and the evidence behind each claim, over MCP and REST.