Tables 27 and 28 interpret ISO 26262-5 Tables 10 and 11 for semiconductors: methods for deriving hardware integration test cases (analysis of requirements as pre- and post-silicon verification of the allocated safety requirements, analysis of the internal and external interfaces through IC integration and IO verification, equivalence classes as test benches by homogeneous feature groups, boundary values, error guessing from design FMEA concerns, functional dependencies, common limit conditions and common cause sources as tests on clock, power, temperature and EMI, and environmental conditions as temperature cycling, soft error rate experiments and high temperature operating life tests) and the corresponding test methods, as a starting point modifiable with rationale.
This control maps to 1 controls across 1 other frameworks. If you already hold one of them, the evidence you collected for it is the starting point here rather than new work.
Every mapping shown was judged rather than inferred from wording similarity, and the ones that failed review are published too. See the coverage reports and what was rejected.
The graph holds this control, the 1 it maps to, and the evidence behind each claim, over MCP and REST.