Figure 3 ties random hardware faults to the chip's failure modes: fault models stand in for physical defects (chosen from the technology and circuit design, because every physical defect cannot be analysed), failure modes are expressed functionally at a granularity that suits the safety concept and its mechanisms, and the share of each failure mode is tied back to the fault models (where X percent of a failure mode comes percent by stuck-at faults and a safety mechanism covers stuck-at faults with Z percent coverage, the claimed diagnostic coverage is X times Z); the distribution of the base failure rate across failure modes is derived accordingly (Annex A gives failure modes for digital circuits).
The graph holds this control, the 0 it maps to, and the evidence behind each claim, over MCP and REST.