A semiconductor component developed as part of an ISO 26262 item is developed on hardware safety requirements derived through the technical safety concept from the item's safety goals, with coverage targets for its relevant failure modes set so the item meets the architectural metrics and either the PMHF or the per-cause (EEC) evaluation, the component being one element among others; to ease distributed development, targets may be given to the chip itself, either SPFM, LFM and PMHF values derived from the item or EEC applied at part level; the safety analysis follows ISO 26262-5 7.4.3 and ISO 26262-9 clause 8, and elements not developed to the standard can be treated under ISO 26262-8 clause 13. The component can be built as an SEooC per ISO 26262-10 on assumptions of use (4.4) that the integrator checks one level up; the part's methods assume an SEooC but remain valid otherwise, and at the stand-alone component level the requirements of parts 2, 5, 6, 7, 8 and 9 (safety analyses, dependent failure analysis, verification) apply.
The graph holds this control, the 0 it maps to, and the evidence behind each claim, over MCP and REST.