Injecting faults into the chip helps to evaluate the architectural metrics and how much of the fault space a safety mechanism covers (software-based hardware tests, hardware built-in self-test), the evaluation of the diagnostic time interval and fault reaction time interval, confirming what a fault actually does (for transient faults, the architectural vulnerability factor), and checking before tape-out that a safety mechanism really catches faults and contains them, corner cases and interconnections included; where accurate results are impractical the campaign can be limited to IP block level, analytical methods used, or both combined; the characteristics to plan are the fault models and abstraction level, the workload, the observation points and the sample size, and the results are interpreted with their statistical confidence.
The graph holds this control, the 0 it maps to, and the evidence behind each claim, over MCP and REST.