The base (raw) failure rate is the primary input to the quantitative safety analyses and metrics of ISO 26262-5 and concerns random hardware failures only; each estimation technique assumes a set of failure mechanisms, so results from different techniques are not comparable unless harmonised on one shared set of mechanisms and stresses; failure mechanisms depend on circuit type, technology and environment, and since published sources lag deep-submicron technology, JEDEC, IRDS and SEMATECH/ISMI publications give the state of the art; the permanent base failure rate calculation methods, the distribution of the failure rate across parts and subparts by area or transistor count, and the transient failure rate for soft errors are described with worked examples.
This control maps to 1 controls across 1 other frameworks. If you already hold one of them, the evidence you collected for it is the starting point here rather than new work.
Every mapping shown was judged rather than inferred from wording similarity, and the ones that failed review are published too. See the coverage reports and what was rejected.
The graph holds this control, the 1 it maps to, and the evidence behind each claim, over MCP and REST.