The hardware architecture is evaluated on its SPFM and LFM against ASIL-dependent targets (part 11 4.1 names the SPFM, LFM and PMHF targets that can be derived at item level or allocated to a semiconductor), the evaluation resting on the classification of each hardware element's faults as single-point, residual, multiple-point (detected, perceived or latent) or safe with their failure rates and diagnostic coverage, as part 10 clause 8 illustrates; the evaluation is verified. Clause 8's aim, as the SGS assessment report quotes it, is evidence from the hardware architectural metrics that the architecture detects and controls safety-related random hardware failures adequately; the report names the analysis of the architecture's effectiveness and its verification review as the audited activities. Requirement text not held.
This control maps to 1 controls across 1 other frameworks. If you already hold one of them, the evidence you collected for it is the starting point here rather than new work.
Every mapping shown was judged rather than inferred from wording similarity, and the ones that failed review are published too. See the coverage reports and what was rejected.
The graph holds this control, the 1 it maps to, and the evidence behind each claim, over MCP and REST.