COTS IP (soft RTL, firm netlist or hard layout IP inserted by the applicant into a custom device for DAL A to C functions, excluding hard IP built into an FPGA by its manufacturer) is selected only if it is technically suitable for the function; its architecture or design concept description explains functionality, modes, configuration and source formats; its data (datasheets, application notes, user guide, errata) allows understanding, integration and verification of all functions, modes and behaviour; information exists to build its physical implementation (synthesis constraints, usage and performance limits, routing instructions); and it can be shown to fulfil its intended function.
This control maps to 1 controls across 1 other frameworks. If you already hold one of them, the evidence you collected for it is the starting point here rather than new work.
Every mapping shown was judged rather than inferred from wording similarity, and the ones that failed review are published too. See the coverage reports and what was rejected.
The graph holds this control, the 1 it maps to, and the evidence behind each claim, over MCP and REST.